1. Field of the Invention
The present invention relates to a method for manufacturing a liquid crystal display device, and in particular to a method for manufacturing a fringe field switching mode liquid crystal display device which can reduce a manufacturing time and cost.
2. Description of the Background Art
An in-plane switching (IPS) mode liquid crystal display device has been suggested to improve a narrow field angle of a TN mode liquid crystal display device. As publicly known, in the IPS mode liquid crystal display device, a counter electrode and a pixel electrode for driving a liquid crystal are aligned in parallel on an identical substrate. The field angle is improved according to a major axis of liquid crystal molecules, regardless of a direction in which a user watches a screen. The IPS mode liquid crystal display device has a wider field angle than the TN mode liquid crystal display device. However, the counter electrode and the pixel electrode consist of an opaque metal, and thus its aperture ratio and transmittance are poor.
Accordingly, in order to improve the aperture ratio and transmittance of the IPS mode liquid crystal display device, there has been taught a fringe field switching mode liquid crystal display device(hereinafter, referred to as xe2x80x98FFS mode LCDxe2x80x99) wherein the liquid crystal molecules are driven by a fringe field.
In the FFS mode LCD, the counter electrode and the pixel electrode consist of a transparent material such as an indium tin oxide (ITO), and an interval between the counter electrode and the pixel electrode is smaller than an interval between upper and lower substrates. In addition, the counter electrode and the pixel electrode have a sufficient width so that the liquid crystal molecules on the electrodes can be all driven. Since the electrodes consist of the transparent material, the FFS mode LCD obtains a more improved aperture ratio than the IPS mode LCD. Moreover, the light permeability occurs in the electrodes, and thus the FFS mode LCD obtains a more improved transmittance than the IPS mode LCD.
FIG. 1 is a cross-sectional diagram illustrating the lower substrate in the conventional FFS mode LCD. A method manufacturing the FFS mode LCD will now be described with reference to FIG. 1.
An ITO film is deposited on a glass substrate 1. The ITO film is patterned according to a first photolithography process, thereby forming a counter electrode 2 in a plate shape. An MoW film is deposited on the counter electrode 2 and the glass substrate 1 and then the MoW film is patterned according to a second photolithography process, thereby forming a gate bus line 3 and a common electrode line 4.
A gate insulating film 5 is formed over the resultant structure. An undoped amorphous silicon film and a doped amorphous silicon film are sequentially deposited on the gate insulating film 5 and then the doped amorphous silicon film and the undoped amorphous silicon film are patterned according to a third lithography process, thereby forming an ohmic contact layer 7 and a channel layer 6. A metal film for source/drain is deposited over the resultant structure. The metal film is patterned according to a fourth lithography process, thereby forming a data bus line(not shown) including source and drain electrodes 8a, 8b. As a result, a thin film transistor (TFT) is formed.
A passivation film 9 is deposited over the resultant structure. Thereafter, the passivation film 9 is etched according to a fifth photolithography process so that the source electrode 8a can be partially exposed. An ITO film is deposited on the passivation film 9 and then patterned according to a sixth photolithography process, thereby forming a comb-shaped pixel electrode 10 having a few branches and contacting with the source electrodes 8a of the TFT.
However, the conventional method for manufacturing the FFS mode LCD has a disadvantage in that six photolithography processes are performed to form the lower substrate, which results in an increased manufacturing time and cost.
In more detail, the photolithography process includes a process for forming a resist pattern such as resist coating, exposure and development processes, an etching process using the resist pattern, and a process for removing the resist pattern. Therefore, even one photolithography process takes a long time. Accordingly, the conventional method for manufacturing the FFS mode LCD by performing the six photolithography processes is not advantageous in productivity. In addition, the etching process requires a mask for exposure that is very expensive. Thus, the six photolithography processes require six masks for exposure. As a result, the conventional method for manufacturing the FFS mode LCD is not advantageous in cost, either.
Therefore, an object of the present invention is to provide a method for manufacturing a fringe field switching mode liquid crystal display device which can reduce a manufacturing time and cost.
In order to achieve the above-described object of the present invention, a method for manufacturing a fringe field switching mode liquid crystal display device includes the steps of: forming a counter electrode, a gate bus line and a common electrode line at the same time, by sequentially depositing an indium tin oxide film and an MoW film on a glass substrate, and patterning the MoW film and the ITO film according to a first photolithography process; depositing a gate insulating film over the resultant structure; forming a stacked channel layer and ohmic contact layer on a predetermined portion of the gate insulating film, by using a second photolithography process; forming a data bus line including source/drain electrodes on the ohmic contact layer and the gate insulting film, by using a third photolithography process; forming a passivation film to expose the source electrode over the resultant structure, by using a fourth photolithography process; and forming a pixel electrode of a comb shape in contact with the source electrode on the passivation film, by using a fifth photolithography process, wherein the first photolithography process comprises: a first process for coating a resist film on the MoW film; a second process for forming a resist pattern consisting of first and second patterns respectively covering gate bus line and common electrode line formation regions and maintaining a coating thickness, and a third pattern covering a counter electrode formation region and partially maintaining the coating thickness, by exposing and developing the resist film; a third process for forming the gate bus line and the common electrode line by dry-etching the MoW film using the resist pattern as an etch barrier, the first and second patterns being partially removed, the third pattern being completely removed, the MoW film on the counter electrode formation region being partially removed; a fourth process for forming the counter electrode by wet-etching the ITO film using the remained resist pattern and MoW film as an etch barrier; and a fifth process for removing the remained resist pattern and MoW film.